An SRAM (Static Random Access Memory) is a type of a semiconductor memory, and stores data by using a flip flop. For example, in the SRAM, data (“1” or “0”) is stored in two cross-connected inverters of complementary MISFETs configured of four MISFETs. Also, two MISFETs are required for the read/write access, and therefore, a memory cell is configured of six MISFETs in a typical SRAM.
Further, in order to achieve a high performance such as low power consumption and high speed of an LSI (Large Scale Integration) including the above-described memory cell or others, employment of an SOI (Silicon On Insulator) substrate has been studied. For example, there is a technique for adjusting a threshold value of a transistor by employing a so-called double gate structure in which the SOI substrate is used for the above-described complementary MISFET (also referred to as CMOS).
For example, Patent Document 1 (Japanese Patent Application Laid-Open Publication No. 1109-266259) described below discloses an SRAM in which N-type semiconductor layers 9-1 and 9-2 are provided in a P-type semiconductor layer 1 below a buried silicon oxide film 2 of an SOI substrate and are connected to gate electrodes 12 (g1) and 12 (g2) of driving transistors T1 and T2. Moreover, it discloses a first contact hole C1 (buried plug) connected to the above-described first N-type semiconductor layer 9-1 and second N-type semiconductor layer 9-2 (see FIG. 4, paragraphs [0025] to [0035], and others).
Further, Patent Document 2 (Japanese Patent Application Laid-Open Publication No. 2008-205322) described below discloses a semiconductor integrated circuit “1” including a memory “4” and a logic circuit “5” which are embedded on a silicon substrate “2”. The above-described memory includes a partially-depleted type nMOS “6” having an SOI structure formed on UTB “3”, and the partially-depleted type nMOS includes a back gate region “14” to which a voltage can be applied independently from a gate terminal, below the UTB. Also, the above-described logic circuit includes fully-depleted type nMOS “7” and pMOS “8” having the SOI structure formed on the UTB, and these fully-depleted type nMOS and pMOS include back gate regions (14, 22) to which a voltage can be applied independently from a gate terminal, below the UTB. Further, this Patent Document 2 also discloses a semiconductor integrated circuit 1A in which a memory 4 formed of a partially-depleted (PD) type nMOS having the SOI structure, a logic circuit 5 formed of fully-depleted type (FD) nMOS 7 and pMOS 8 having the SOI structure, and an input protection element 50 formed of an nMOS 51 and a pMOS 52 having a bulk structure are embedded on a silicon substrate 2 (see FIG. 10, paragraphs [0044] to [0046], and others).